The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Digital-to-analog converters (DACs) receive a digital input signal and convert the digital input signal into an analog output signal. The digital input signal has a range of digital codes that are converted into a continuous range of analog signal levels of the analog output signal. Accordingly, DACs are typically used to convert data between applications operating in digital and analog domains. For example only, applications of DACs include, but are not limited to, video display drivers, audio systems, digital signal processing, function generators, digital attenuators, data storage and transmission, precision instruments, and data acquisition systems.
A variety of types of DACs are available based upon desired functionality. For example only, DACs may have varying predetermined resolutions of the digital input signal, receive different encoded digital input signals, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Various DAC performance factors include, but are not limited to, settling time, full scale transition time, accuracy or linearity, and resolution.
A number of bits (i.e. a bit width) of the digital input signal defines the resolution, a number of output (quantization) levels, and a total number of digital codes that are acceptable for the DAC. For example, if the digital input signal is m-bits wide, the DAC has 2m output levels.
Referring now to FIG. 1, an example DAC 10 includes a ladder module 12 having m ladder bits and a switch control module 14. For example only, the ladder module 12 is an R-βR ladder. When β=2, the R-βR ladder may be referred to as an R-2R, or binary radix, ladder, corresponding to a binary radix DAC. In a binary radix DAC, the ratio of a DAC element to a next (lower) DAC element is 2. When 13 is greater than or less than 2, the ladder may be referred to as a non-binary ladder. For example, in a sub-binary radix (i.e. sub-radix2) ladder (corresponding to a sub-binary radix DAC), the ratio of a DAC element to a next lower DAC element is a constant greater than 2 (i.e. sub-binary). For example only, the ratio may be approximately 2.5, which would set the radix of the DAC to a sub-binary value approximately equal to 1.85.
The ladder module 12 receives analog reference signals 16 and 18. For example only, the analog reference signal 16 may be ground and the analog reference signal 18 may be a positive reference voltage. The switch control module 14 receives bits b0, b1, . . . , bm-1 of an m-bit binary digital input signal 20 and controls switches (not shown) of the ladder module 12 based on the m bits of the digital input signal 20. The ladder module 12 generates an analog output signal 22 based on the digital input signal 20 (i.e. the controlled switches of the ladder module 12) and the analog reference signals 16 and 18. Accordingly, the analog output signal 22 corresponds to the digital-to-analog conversion of the digital input signal 20.
Referring now to FIG. 2, the ladder module 12 of the DAC 10 is shown to include resistors RL0 . . . RLm-1, referred to collectively as RLi, and resistors RDL0 . . . RDLm-1, referred to collectively as resistors RDLi. Each of the resistors RLi has a value R and each of the resistors RDLi has a value βR. In other words, β corresponds to a ratio of an RDL resistor value to an RL resistor value. A termination resistor RT has a value of γR. The values of β and γ satisfy the equation γ2=β+γ. The analog reference signals 16 and 18 are selectively provided to the resistors RT and RDLi via switches 30.
Referring now to FIG. 3, the switch control module 14 includes a switch regulator module 40 and a switch driver module 42. The switch regulator module 40 receives the analog reference signals 16 and 18 and generates a gate driver signal 44 having a voltage VGN. The switch driver module 42 receives the gate driver signal 44, the analog reference signal 18, and the m-bit binary digital input signal 20. The switch driver module 42 generates a plurality of switch control signals 46 to control the switches 30 based on the gate driver signal 44, the analog reference signal 18, and the m-bit binary digital input signal 20. For example only, the switch driver module 42 may implement a cascaded inverter that selectively outputs the gate driver signal 44 and the analog reference signal 18 according to the m-bit binary digital input signal 20. For example, the gate driver signal 44 may be used to control the switches 30 that include N-type transistors. Conversely, the analog reference signal 18 may be used to control the switches 30 that include P-type transistors.
Bits of the ladder module 12 are set or cleared based on the switch control signals 46 input to the switches 30. For example, a bit may correspond to an adjacent pair of the switches 30 including an N-type transistor and a P-type transistor. The bit may be set when one of the switches 30, connected to the analog reference signal 18, is closed and the other of the switches 30, connected to the analog reference signal 16, is open. Conversely, the bit may be cleared when the one of the switches 30 connected to the analog reference signal 16 is open and the other of the switches 30 connected to the analog reference signal 16 is closed.
Referring now to FIG. 4, the switch regulator module 40 includes first and second switches 50 and 52 (e.g., first and second transistors, respectively), an operational amplifier 54, and resistors 56, 58, 60, and 62. Each of the resistors 56 and 58 has a value Rx and each of the resistors 60 and 62 has a value Ry. The switch regulator module 40 regulates the gate driver signal 44 using a negative feedback loop such that the on resistances of any given pair of the switches 30 (e.g., the N-type transistor and the P-type transistor corresponding to any bit) are equal. In this manner, the regulated gate driver signal 44 is used to drive the gates of all of the switches 30 corresponding to N-type transistors, and the analog voltage reference 18 drives the gates of the switches 30 corresponding to P-type transistors. Conversely, in other implementations the switch regulator module 40 could instead generate the gate driver signal 44 for the switches 30 corresponding to P-type transistors, and the analog voltage reference 18 could be used to drive the gates of the switches 30 corresponding to N-type transistors. In other implementations, only N-type transistors or only P-type transistors may be used.
As shown in FIG. 2, aspect ratios of the sizes of the switches 30 are scaled up from a least significant bit (LSB) to a most significant bit (MSB). In other words, the aspect ratios of the switches 30 are scaled up from right to left. Accordingly, on resistances of the switches 30 are scaled down from right to left. As the number of bits in the ladder module 12 increases, the size of each additional MSB switch increases exponentially, resulting in increased die size and increased sensitivity to layout parasitic resistance and/or capacitance.
Typically, on resistances of the switches 30 are minimized to reduce linearity degradation caused by on resistance mismatch and drift. Further, the switches 30 corresponding to the LSBs of the ladder module 12 are kept small enough such that the switches 30 are not forced into a saturation region. Accordingly, the switches 30 are selected to minimize the on resistances of the LSB switches, which corresponds to increased die size, to prevent the switches 30 from entering the saturation region and causing linearity degradation. The limitations on the on resistance as well as the scaling of the switches 30 can result in prohibitively large MSB switches.